1. Technical Field
The present disclosure relates to the field of clock signal generation, and more particularly to the generation of multiple phase-aligned clock signals.
2. Related Art
In an ideal synchronous circuit, all data transitions occur simultaneously and all components are synchronized by one or more related clock signals. Multiple clock signals are often used in a circuit because circuit components are designed to function (reliably) at different speeds. For example, a central processing unit (CPU) typically functions at a much higher speed than a peripheral/external interface data bus. It is important, however, that the frequency of the clock signal that drives the CPU be a multiple of the frequency of the clock signal that drives the data bus so that data bus operations are in synchronization with the operation of the CPU. For example, a CPU may function at 3 GHz and the system bus may function at 375 MHz, a ratio of 1:8. Operations that involve both the CPU and the data bus will succeed only if (1) the CPU and data bus clock signals maintain the 1:8 ratio and (2) each data bus clock signal transition occurs at the same time with respect to eight CPU clock signals, i.e., the CPU and data bus clock signals are phase-aligned.
High speed components and increasingly complex circuits have made it difficult to phase-align the different clock signals in a circuit. In addition, some circuits require three, four, or even more different clock signals, all of which must be phase-aligned. In such circuits, phase-alignment is partially aided by having all of the clock circuits (also referred to as clock dividers) derive their clock signals (also referred to as clock root signals) from a common signal, typically generated by a phase-locked loop (PLL) system. The PLL system, in turn, is driven by a chip's reference clock oscillator. Thus, all clock root signals are derived, either directly or indirectly, from a common reference clock oscillator.
One of the factors that determines the complexity of the clock dividers is the number of different clock root signals that must be phase-aligned. The greater the number of clock root signals, the less forgiving each clock divider can be to clock signal effects such as skew, jitter, and noise. Stability, predictability, and variance parameters of clock dividers are becoming increasingly stringent due to circuit designs that utilize high speed components and multiple clock root signals.
One technique for generating phase-aligned clock root signals is to “merge” the clock dividers into the PLL system design. However, this design approach typically involves highly sensitive analog and digital design considerations and leads to difficult verification and qualification processes.
Another technique for generating phase-aligned clock root signals is to provide the PLL system output to a series of cascaded multiplexer circuits, and have each multiplexer provide a different clock root signal. However, this design approach leads to long signal paths of varying lengths and, consequently, high jitter. It also requires large timing margins. An improved approach is desirable.